Generally, semiconductor memory devices are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices according to whether a power supply is required to maintain stored data. Volatile semiconductor memory devices, such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device, operate at high speeds, and they require power supplies to maintain their stored data. On the other hand, nonvolatile semiconductor memory devices, such as a phase changeable random access memory (PRAM) device, a metal oxide resistive random access memory (RRAM) device, or a ferroelectric random access memory (FRAM) device, do not require a power supply to maintain their stored data.
The RRAM device may have a cell capacitor including a transition metal oxide instead of a dielectric layer of the DRAM cell capacitor. The resistance of the transition metal oxide can be changed according to a programmed voltage applied to top and bottom electrodes of the transition metal oxide. The resistivity of the transition metal oxide can change more than one hundred times depending on the magnitude of the programmed voltage, and the transition metal oxide can maintain the changed resistivity even when the programmed voltage is interrupted. Data stored in the transition metal oxide may be gathered to determine whether the data is logic “1” or logic “0” by sensing the change in voltage and current caused by a difference of the resistivity.
FIG. 1 is a cross-sectional view of a conventional nonvolatile memory device. FIGS. 2 through 4 are graphs illustrating a switching characteristic of a conventional nonvolatile memory device.
Referring to FIG. 1, a gate pattern 25 is disposed on a semiconductor substrate 10. The gate pattern 25 may include a gate insulating layer 22 and a gate electrode 24. Source and drain regions 12 and 14 are disposed in the substrate 10 adjacent to the gate pattern 25. A first insulating interlayer 20 is disposed on the substrate 10 to cover the gate pattern 25. A contact plug 26 is disposed in the first insulating interlayer 20 and is connected to the drain region 14.
A bottom electrode 32 is disposed on the first insulating interlayer 20 and is connected to the contact plug 26. The bottom electrode 32 may include iridium (Ir). A data storage layer 34 is disposed on the bottom electrode 32. The data storage layer 34 may include nickel oxide (NiO). A top electrode 36 is disposed on the data storage layer 34. The top electrode 36 may include iridium (Ir). A second insulating interlayer 30 is disposed on the first insulating interlayer 20 to cover the top electrode 36. A plate electrode 40 is disposed on the second insulating interlayer 30 and is connected to the top electrode 36.
FIGS. 2 through 4 illustrate graphs obtained for a nonvolatile memory device in which the top and bottom electrodes include iridium (Ir) and the data storage layer 34 includes nickel oxide (NiO). FIG. 2 shows a set resistance and a reset resistance of the memory device having the transition metal oxide. FIG. 3 is a histogram showing a distribution of the set and reset resistances shown in FIG. 2. In FIG. 4, the horizontal axis shows the number of cycles of program and erase, and the vertical axis shows the set and reset resistances. In FIGS. 2 and 3, the range of the set and reset resistances is wide, and the difference between the set and reset resistances is almost one thousand times. The distribution of the set/reset resistances is not uniform. As a result, a conventional nonvolatile memory device may not provide a stable switching operation.